1.2.6

• Fixed issues with support java 1.5


• Fixed issues with SV Macros


• Added Support for VHDL Emacs copy mode


• Added Error Highlighting from External Tools

1.2.5

• Fixed issues with SV Macros


• Added State Machine Generator

1.2.4

• Added Basic Indenting Engine


• Added Support for Project Created From Xilinx .prj Format


• Fixed Minor Verilog Documentation Issues

1.2.3

• Added Wizard for Creating and Importing Projects


• Cleaned up some Memory Issues

1.2.2

• Many Small Improvements to System Verilog


• Improved Support for Functions


• New Wizard for Creating Simple Veriog Suite


• Fixed Issues with Library Files Not Showing in Editor

1.2.1

• Fixed Issue with Java 1.5
• Fixed Issues with Highlight Select
• Added Dialog to Ignore Large Files
• Added Python Menu to Editor
• Made Emacs Command Configurable by User Preference
• Added Basic Support for ISIM
• Fixed Issue with End of Line Comments for Pop Up Documentation

1.2.0

• Added Support for TODO tasks
• Added Support for Natural Docs SV documentation
• Fixed issue related to VHDL completion
• Fixed Click Highlight Issue for Architecture and Package Names

1.1.62

• Fixed System Verilog Function Completion Prepending (
  
• Fixed Issue with Split File Editting
  
• Fixed Issue with Project Structure
  
• Added Hyperlinks showing where module is instatiated
  

1.1.60

• Fixed Issues with VHDL Click Highlight for Arrays
  
• Fixes Issues with Click Highlight Stability
  
• Cleaned up some Port Refactoring Issues
  
• Added Support for Projects with a File List
  
• Added Coloring for UCF Files
  

1.1.59

• Improved Support for System Verilog Interfaces
  
• Added Support for Verilog Generate Statements
  
• Added Unisim Libraries
  

1.1.58

• Fixed an issue with editting files outside of the workspace
  
• Added Project Selection for New Component Insertion
  

1.1.56

• Added Support for Embedded Python Templates
  
• Fixed Issue with ModelSim Interfaces
  
• Fixed Issue with Verilog Ports in Outline View
  
• Fixed Issue with Annotation Error
  
• Fixed Issues with Automatic Instantiation
  
• Fixed Issue with search not finding Outputs and Regs with the same name
  

1.1.54

• Added Xilinx Example Suite
  
• Fixed Python Interfaces
  

1.1.53

• Fixed Issue With Library Files on Linux
  

1.1.52

• Made Single file Libraries the Default Method of Operations
• Added Example Projects for SystemVerilog (OVM, UVM, VMM)

1.1.51

• Fixed Some Issue with Project
  Navigator New Menu's
• Removed Component's from
  Completion inside Instantiation
• Fixed Some Performance Issue's with Libraries

1.1.50

• Added More Fixes for Libraries
• Fixed Issue with Completion with
  no Prefix
• Fixed Issue with New Instance Wizard

1.1.49

• Added Improved Way to Handle
  Standard Libraries (ieee, std, unisim, ...) for VHDL in a Single File. The Documentation will be added shortly
• Fixed an Issue with Templates
• Added a Popup Menu to Connect Signals in the New Instance
  Menu

1.1.48

• Continued Improvement of System
  Verilog Functionality
• Addition of Quick View Displays
  (Hierarchy/Class Hierarchy/Outline)
• Added Support for creating Instance and Component
• Fixed Issue with Key Bindings
• Fixed Issue with Find Highlight Feature

1.1.38

• Continued Improvement of System Verilog Functionallity
• Bug Fix To Fully Support Files with .sv and .svh Extensions
• Large Cleanup of Multiple VHDL Completion and Documentation Issues
• Improvement of Formatting Issues with Templates
• Context Sensitive Completion added for Many VHDL Constructs

1.1.33

• Cleanup of Issues with VHDL Capitalization
• Cleanup of SystemVerilog/Verilog Variable Documentation
• Addition of Completion inside SystemVerilog Functions and Classes

1.1.32

• Added a Directory to Automatically Configure Directory Structures and Templates
• Added support for SystemVerilog variables which are Clases or Interfaces

1.1.30

• Added Support for Commpletion inside a VHDL Function
• Fixed hanging issue when using hyperlinks to opening a large file
• Added some Support for Completion inside SV classes and instances
• Fixed Issue with Hyperlinks of Include Files

1.1.29

• Fixes for Stack Overflow with a Library and Package of the Same Name

1.1.28

• Added Support for comments on the end of line of types to be used in the documentation
• Fixed a double click issue for Verilog
• Added New View showing a list of "Modules/Packages/..." in the Design
• Completed Rudimentary Support for System Verilog

1.1.27

• Added Un/Capitalize Actions for VHDL
• Added Support for Refactoring Enumerations
• Fixed Issues related to Completion Stability
• Added Support for more SystemVerilog Constructs

1.1.26

• Fixed Issue with Verilog Functions
• Added Support for more SystemVerilog Constructs

1.1.25

• Made improvements for error recovery
• Added Support for some SystemVerilog Constructs

1.1.24

• Added Better Support for Verilog Generate Statements
• Added Better Support and Folding for Verilog compiler directives
• Fixed some issues with double click options

1.1.22

• Fixed Code Folding on Block Statements in VHDL
• Allowed comments after variable declarations to be used for text hovers
• Fixed Code Folding on Generate Statements in Verilog
• Added support for attributes (* ... *)

1.1.21

• Fixed Completion Issues inside functions and process statements
• Made fixes to port connect refactorings


• Add Port
• Remove Port
• Connect Ports



• Added a new context menu (New)


• New Instance
• New Component
• New Entity/Module

1.1.20

• Fixed issue with verilog "automatic" function
• Fixed issuse with non local task and function calls ie cpu.read()
• Improved support for automatic instantiation entities/modules
• Added support for connecting ports with generate statements
• Added support for finding references in generate statements

1.1.19

• Fixed issue with support for ansi port task and functions
• Fixed issue with task calls with no arguments
• Added type completion to Add/Remove Ports Refactoring
  

1.1.18

• Completion Fixes
  
  • Ports always were prefaced with a (
  
  
  • Completion right after a ( failed occasionally
  • Completion continues to work after a parse error

  
  
• Reference Path To and Path From added
• `default_net_type none now supported
• ' and ` now added to the punctuation list for coloring

1.1.17

• Emacs Auto Modes
• Various Fixes Related to VHDL completion operations
• Enhancements to configurable directory structure
• Fixes to outline view when syntax error occurs