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State Machine Generator
One of the templates included is a state machine generator which creates a standard synopsys recommended state machine. There is a very simple language describing the state machine which allows the state machine to be designed more easily and more importantly to be easily understood by future users. A very simple example is shown below for verilog.
one_hot false
clock_head beta
current_state "state"
next_state "next_state"
transition A -> B : case("count[1:0]") "2'b0"
-> C : "2'b1"
-> D :
B -> A : "count == 20"
-> C : "count == 25"
-> D :
The syntax should be very straightforward. The initial commands are optional and define required parameters to create the register and defines the state variables. The clock_head is used to define the type of flop and is defined in a separate piece of simple code to make reuse easier. The transition syntax defines the initial state and the conditions to transition to the next state. This condition can either be a case statement or a standard if expression. The generated code for this simple example is shown below.
Please note that the purpose of this tool is
not to help in architectural definition but just to simplify the mundane error
prone process of coding the design.
/* AUTO GENERATED (DO NOT EDIT MANUALLY) */
always @* begin
case(state)
A :
case(count[1:0])
2'b0 : next_state
= B;
2'b1 : next_state
= C;
default : next_state = D;
endcase
B :
if (count == 20) begin
next_state =
A;
end
else if (count == 25) begin
next_state =
C;
end
else begin
next_state =
D;
end
endcase
end
always @(posedge clk or negedge reset) begin
if (!reset) begin
state <= A;
end
else begin
state <=
next_state;
end
end
/*
END AUTOGENERATION */
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