SimplifIDE is developing tools that bring the power of software development environments to the hardware design languages VHDL and Verilog. Our goal is to simplify and automate the mundane tasks of design engineers so that they can spend more time doing architecture work. Our initial product is a plugin for eclipse which brings the enhanced productivity of a software design environment to writing HDL. This product has been in development for several years and has been used in the development of high volume ASICs/FPGAs and ICs.
This product has been easily customized based on user requirements and has supported many different features ranging from automatic document generation to advanced DSP IP generation. Currently we have a stable product for VHDL and Verilog shown below which contains many advanced editing features (rapidly being expanded as we continue to port features from our existing toolset).
Simplifide has recently become free for all users. We are also licensing the source code for both enterprise customers who would like to customize it for their internal use as well as companies who are looking for an editor or front end for their tools. Please contact us for details.
Our first product is a VHDL and Verilog plugin for eclipse which supports standard advanced software editing features, but targetted towards hardware design.
ScalaDL is an an internal DSL for Scala which supports hardware languages. It is now publicly released and ready for use.